86 lines
2.0 KiB
VHDL
86 lines
2.0 KiB
VHDL
-- In this test, we declare a component in the "gates" package
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-- and show that it can be referenced within the package namespace.
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library ieee;
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use ieee.numeric_bit.all;
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package gates is
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-- full 1-bit adder
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component fa1 is
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port (a_i, b_i, c_i: in bit;
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s_o, c_o: out bit);
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end component fa1;
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end package gates;
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-- Declare and implement a 4-bit full-adder that uses the
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-- 1-bit full-adder described above.
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entity fa4 is
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port (va_i, vb_i: in bit_vector (3 downto 0);
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c_i: in bit;
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vs_o: out bit_vector (3 downto 0);
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c_o: out bit
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);
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end entity fa4;
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architecture fa4_rtl of fa4 is
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use work.gates.fa1;
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-- internal carry signals propagation
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signal c_int: bit_vector (4 downto 0);
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begin
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-- carry in
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c_int(0) <= c_i;
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-- slice 0
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s0: fa1 port map (c_i => c_int(0),
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a_i => va_i(0),
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b_i => vb_i(0),
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s_o => vs_o(0),
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c_o => c_int(1)
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);
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-- slice 1
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s1: fa1 port map (c_i => c_int(1),
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a_i => va_i(1),
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b_i => vb_i(1),
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s_o => vs_o(1),
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c_o => c_int(2)
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);
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-- slice 2
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s2: fa1 port map (c_i => c_int(2),
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a_i => va_i(2),
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b_i => vb_i(2),
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s_o => vs_o(2),
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c_o => c_int(3)
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);
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-- slice 3
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s3: fa1 port map (c_i => c_int(3),
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a_i => va_i(3),
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b_i => vb_i(3),
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s_o => vs_o(3),
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c_o => c_int(4)
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);
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-- carry out
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c_o <= c_int(4);
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end architecture fa4_rtl;
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-- Declare a 1-bit full-adder.
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entity fa1 is
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port (a_i, b_i, c_i: in bit;
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s_o, c_o: out bit
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);
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end entity fa1;
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architecture fa1_rtl of fa1 is
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begin
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s_o <= a_i xor b_i xor c_i;
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c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
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end architecture fa1_rtl;
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