32 lines
487 B
Verilog
32 lines
487 B
Verilog
/*
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* This module instantiates the fa4 entity, which in turn
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* instantiates other entities. This demonstrates hierarchical
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* constructs in VHDL.
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*/
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module test;
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reg [3:0] a, b;
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reg cin;
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wire [3:0] s;
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wire cout;
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initial begin
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cin = 0;
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a = 4'h2;
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b = 4'h3;
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end
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initial begin
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#1;
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if (s !== 4'h5) begin
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$display("Error in trivial sum");
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$finish;
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end
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$display ("PASSED");
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end
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fa4 duv (.c_i(cin), .va_i(a), .vb_i(b), .vs_o(s), .c_o(cout) );
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endmodule // test
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