20 lines
437 B
VHDL
20 lines
437 B
VHDL
-- This VHDL was converted from Verilog using the
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-- Icarus Verilog VHDL Code Generator 0.10.0 (devel) (s20090923-519-g6ce96cc)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity subtract is
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port (
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a : in unsigned(3 downto 0);
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b : in unsigned(3 downto 0);
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out_sig : out unsigned(3 downto 0)
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);
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end entity;
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architecture test of subtract is
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begin
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out_sig <= (a + not b) + 1;
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end architecture;
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