23 lines
471 B
Verilog
23 lines
471 B
Verilog
module main;
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wire [3:0] a, b;
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wire [3:0] out;
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subtract dut (.a(a), .b(b), .out_sig(out));
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reg [8:0] test_vector;
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assign {a, b} = test_vector;
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initial begin
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for (test_vector=0 ; test_vector[8]==0 ; test_vector=test_vector+1) begin
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#1 if (out != a-b) begin
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$display("FAILED -- out=%b, expecting %b-%b=%b", out, a, b, a-b);
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$finish;
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end
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end
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$display("PASSED");
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$finish;
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end // initial begin
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endmodule // main
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