76 lines
2.8 KiB
VHDL
76 lines
2.8 KiB
VHDL
-- Copyright (c) 2015 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Test for accessing constant records & arrays of records in VHDL.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity vhdl_const_record is
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port(sel : in integer range 0 to 3;
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hex : out std_logic_vector(7 downto 0);
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aval : out std_logic_vector(7 downto 0));
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end entity vhdl_const_record;
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architecture test of vhdl_const_record is
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type t_var is (var_presence, var_identif, var_1, var_2, var_3, var_rst, var_4, var_5, var_whatever);
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type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
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type t_var_record is record
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var : t_var; -- 32 bits
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a : t_byte_array (3 downto 0); -- 4*8 bits
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hexvalue : std_logic_vector (7 downto 0); -- 8 bits
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end record; -- total 72 bits
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type t_var_array is array (natural range <>) of t_var_record;
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constant c_vars_array : t_var_array(0 to 3) := (
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0 => (var => var_presence,
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hexvalue => x"14",
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a => (0 => x"aa", 1 => x"ab", 2 => x"ac", 3 => x"ad")),
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1 => (var => var_identif,
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hexvalue => x"24",
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a => (0 => x"ba", 1 => x"bb", 2 => x"bc", 3 => x"bd")),
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2 => (var => var_1,
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hexvalue => x"34",
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a => (0 => x"ca", 1 => x"cb", 2 => x"cc", 3 => x"cd")),
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3 => (var => var_2,
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hexvalue => x"56",
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a => (0 => x"da", 1 => x"db", 2 => x"dc", 3 => x"dd"))
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);
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constant c_record : t_var_record := (
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var => var_4,
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hexvalue => x"66",
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a => (0 => x"00", 1 => x"11", 2 => x"22", 3 => x"33")
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);
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signal sig : std_logic_vector(7 downto 0);
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signal sig2 : std_logic_vector(7 downto 0);
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begin
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sig <= c_record.hexvalue;
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process(sel)
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begin
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sig2 <= c_record.a(sel);
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hex <= c_vars_array(sel).hexvalue;
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aval <= c_vars_array(sel).a(sel);
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end process;
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end architecture test;
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