71 lines
1.6 KiB
Verilog
71 lines
1.6 KiB
Verilog
// Copyright (c) 2015 CERN
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// Maciej Suminski <maciej.suminski@cern.ch>
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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// Test for accessing constant records & arrays of records in VHDL.
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module vhdl_const_record_test;
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int sel;
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logic [7:0] hex;
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logic [7:0] aval;
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vhdl_const_record dut(sel, hex, aval);
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initial begin
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if(dut.sig !== 8'h66)
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begin
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$display("FAILED 1");
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$finish();
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end
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sel = 0;
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#1;
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if(hex !== 8'h14 || aval !== 8'haa || dut.sig2 !== 8'h00)
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begin
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$display("FAILED 2");
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$finish();
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end
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sel = 1;
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#1;
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if(hex !== 8'h24 || aval !== 8'hbb || dut.sig2 !== 8'h11)
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begin
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$display("FAILED 3");
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$finish();
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end
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sel = 2;
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#1;
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if(hex !== 8'h34 || aval !== 8'hcc || dut.sig2 !== 8'h22)
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begin
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$display("FAILED 4");
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$finish();
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end
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sel = 3;
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#1;
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if(hex !== 8'h56 || aval !== 8'hdd || dut.sig2 !== 8'h33)
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begin
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$display("FAILED 5");
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$finish();
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end
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$display("PASSED");
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end
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endmodule
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