60 lines
1.9 KiB
VHDL
60 lines
1.9 KiB
VHDL
-- Copyright (c) 2015 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Test for constant arrays access
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.constant_array_pkg.all;
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entity constant_array is
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port (index : in std_logic_vector(2 downto 0);
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output : out std_logic_vector(7 downto 0));
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end entity constant_array;
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architecture test of constant_array is
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type logic_array is array (integer range <>) of std_logic_vector(0 to 3);
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constant test_array : logic_array(0 to 5) :=
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(0 => "0010",
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1 => "1000",
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2 => "0100",
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3 => "0110",
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4 => "0101",
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5 => "1100");
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-- Check if constant vectors are not broken with the changes
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constant vector : std_logic_vector(5 downto 0) := "110011";
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signal test_a : unsigned(7 downto 0);
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signal test_b : std_logic_vector(3 downto 0);
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signal test_c : std_logic_vector(2 downto 0);
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signal test_d : std_logic;
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begin
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test_a <= const_array(3);
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test_b <= test_array(2);
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test_c <= vector(4 downto 2);
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test_d <= vector(5);
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process (index)
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begin
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output <= const_array(to_integer(unsigned(index)));
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end process;
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end architecture test;
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