42 lines
1.3 KiB
VHDL
42 lines
1.3 KiB
VHDL
-- Copyright (c) 2014 CERN
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-- Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- Test for multiple choices in case alternative statements.
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library ieee;
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use ieee.std_logic_1164.all;
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entity vhdl_case_multi is
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port ( inp: in std_logic_vector (0 to 2);
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parity: out std_logic );
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end vhdl_case_multi;
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architecture vhdl_case_multi_rtl of vhdl_case_multi is
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begin
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process (inp)
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begin
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case inp is
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when "000"|"011"|"101"|"110" => parity <= "0";
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when "001"|"010"|"100"|"111" => parity <= "1";
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when others => parity <= "Z";
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end case;
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end process;
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end vhdl_case_multi_rtl;
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