44 lines
1.3 KiB
VHDL
44 lines
1.3 KiB
VHDL
-- Copyright (c) 2015 CERN
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-- @author Maciej Suminski <maciej.suminski@cern.ch>
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--
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-- This source code is free software; you can redistribute it
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-- and/or modify it in source code form under the terms of the GNU
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-- General Public License as published by the Free Software
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-- Foundation; either version 2 of the License, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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-- boolean values test.
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library ieee;
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entity vhdl_boolean is
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end vhdl_boolean;
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architecture test of vhdl_boolean is
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signal true_val, false_val, and1, and2, and3, or1, or2, or3, not1, not2 : boolean;
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begin
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true_val <= true;
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false_val <= false;
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and1 <= true and true;
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and2 <= true and false;
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and3 <= false and false;
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or1 <= true or true;
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or2 <= true or false;
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or3 <= false or false;
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not1 <= not false;
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not2 <= not true;
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end architecture test;
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