70 lines
1.6 KiB
Verilog
70 lines
1.6 KiB
Verilog
/*
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* Copyright (c) 2001 Brendan J Simon <brendan.simon@bigpond.com>
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// test case to show vector ordering bugs.
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module test;
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reg [4:0] foo40; // works great.
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reg [0:4] foo04; // only works for time=0;
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//reg [4:0] foo04;
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reg [5:1] foo51; // never works.
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//reg [4:0] foo51;
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reg [1:5] foo15; // never works.
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//reg [4:0] foo15;
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initial begin
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#102; $finish(0);
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end
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initial #1 begin
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foo40 = 0;
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foo04 = 0;
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foo51 = 0;
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foo15 = 0;
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end
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always #10 begin
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foo40 <= foo40 + 1;
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foo04 <= foo04 + 1;
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foo51 <= foo51 + 1;
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foo15 <= foo15 + 1;
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end
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always @(foo40) begin
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$write("foo40=%8d\n", foo40);
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end
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always @(foo04) begin
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$write(" foo04=%8d\n", foo04);
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end
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always @(foo51) begin
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$write(" foo51=%8d\n", foo51);
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end
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always @(foo15) begin
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$write(" foo15=%8d\n", foo15);
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end
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endmodule
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