76 lines
1.2 KiB
Verilog
76 lines
1.2 KiB
Verilog
module test;
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reg a, b1, b2;
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submod m1 (a, b1, c1);
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submod m2 (a, b2, c2);
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task set;
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input [2:0] bits;
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reg t1;
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begin
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t1 <= a;
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#1 {a,b1,b2} <= bits;
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end
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endtask
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initial
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begin
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$dumpfile("work/vcd-dup.vcd");
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$dumpvars(2, test); // test, test.m1, test.m2
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$dumpvars(3, m2.c1, m1.mm1.c1); // duplicate signals
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#0; // does not trip $enddefinitions
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a = 0; // does not trip $enddefinitions
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$dumpvars(0, m1); // (test.m1), test.m1.mm1, test.m1.mm2
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#1; // $enddefinitions called
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$dumpvars(0, m2); // ignored
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end
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initial
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begin
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#1 set(3'd 0);
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#1;
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#1 set(3'd 1);
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#1;
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#1 set(3'd 2);
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#1 $dumpoff;
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#1 set(3'd 3);
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#1;
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#1 set(3'd 4);
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#1 $dumpon;
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#1 set(3'd 5);
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#1;
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#1 set(3'd 6);
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#1;
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#1 set(3'd 7);
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#1;
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#1 set(3'd 0);
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#1 $dumpall;
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#1 $finish;
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end
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endmodule
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module submod (a, b, c);
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input a, b;
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output c;
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subsub mm1 (a&b, c1);
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subsub mm2 (a|b, c2);
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assign c = c1 ^ c2;
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endmodule
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module subsub (a, c);
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input a;
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output c;
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wire c1 = ~a;
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assign c = c1;
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endmodule
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