182 lines
4.4 KiB
VHDL
182 lines
4.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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package diq_pkg is
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component Add_Synth
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generic (n: integer);
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port (a,b: in std_logic_vector (n-1 downto 0);
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cin: in std_logic;
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comp : out std_logic;
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sum : out std_logic_vector (n-1 downto 0) );
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end component;
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component Inc_Synth
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generic (n: integer);
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port (a: in std_logic_vector (n-1 downto 0);
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sum : out std_logic_vector (n-1 downto 0) );
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end component;
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end package;
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library ieee;
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use ieee.std_logic_1164.all;
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use work.diq_pkg.all;
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entity diq_array is
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generic (width: integer := 8; size: integer := 7);
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port (clk,reset: in std_logic;
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din,bin,xin: in std_logic_vector (width-1 downto 0);
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lin: in std_logic_vector (2 downto 0);
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lout: out std_logic_vector (2 downto 0);
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dout,bout,xout: out std_logic_vector (width-1 downto 0) );
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end diq_array;
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architecture systolic of diq_array is
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component diq
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generic (n: integer );
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port (clk,reset: in std_logic;
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lin: in std_logic_vector (2 downto 0);
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din,bin,xin: in std_logic_vector (n-1 downto 0);
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lout: out std_logic_vector (2 downto 0);
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dout,bout,xout: out std_logic_vector (n-1 downto 0) );
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end component;
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type path is array (0 to size) of std_logic_vector (width-1 downto 0);
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type l_path is array (0 to size) of std_logic_vector (2 downto 0);
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signal x_path, d_path, b_path: path;
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signal l_int: l_path;
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begin
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gen_arrays: for i in 0 to size-1 generate
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each_array: diq generic map (n => width)
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port map (clk => clk, din => d_path(i), bin => b_path(i), reset => reset,
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xin => x_path(i), lin => l_int(i),
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dout => d_path(i+1), bout => b_path(i+1),
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xout => x_path(i+1), lout => l_int(i+1) );
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end generate;
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d_path(0) <= din;
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b_path(0) <= bin;
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x_path(0) <= xin;
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l_int(0) <= lin;
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dout <= d_path(size);
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bout <= b_path(size);
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xout <= x_path(size);
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lout <= l_int(size);
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end systolic;
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library ieee;
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use ieee.std_logic_1164.all;
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use work.diq_pkg.all;
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entity diq is
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generic (n: integer := 8);
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port (clk, reset: in std_logic;
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din,bin,xin: in std_logic_vector (n-1 downto 0);
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lin: in std_logic_vector (2 downto 0);
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dout,bout,xout: out std_logic_vector (n-1 downto 0);
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lout: out std_logic_vector (2 downto 0) );
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end diq;
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architecture diq_wordlevel of diq is
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signal b_int, d_int, x_int, x_inv: std_logic_vector (n-1 downto 0);
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signal l_int, l_inc: std_logic_vector (2 downto 0);
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signal sel: std_logic;
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signal zero,uno: std_logic;
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begin
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d_reg: process(clk,reset)
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begin
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if reset = '1' then
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d_int <= (others => '0');
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elsif (clk'event and clk = '1') then
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d_int <= din;
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end if;
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end process;
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l_reg: process(clk,reset)
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begin
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if reset = '1' then
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l_int <= (others => '0');
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elsif (clk'event and clk = '1') then
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l_int <= lin;
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end if;
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end process;
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b_reg: process(clk,reset)
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begin
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if reset = '1' then
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b_int <= (others => '0');
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elsif (clk'event and clk = '1') then
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b_int <= bin;
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end if;
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end process;
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x_reg: process(clk,reset)
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begin
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if reset = '1' then
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x_int <= (others => '0');
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elsif (clk'event and clk = '1') then
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x_int <= xin;
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end if;
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end process;
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zero <= '0';
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uno <= '1';
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addition: Add_Synth generic map (n => n)
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port map (a => b_int, b => d_int, cin => zero, comp => open, sum => bout);
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x_inv <= not x_int;
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comparison: Add_Synth generic map (n => n)
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port map (a => b_int, b => x_inv, cin => uno, comp => sel, sum => open);
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incrementer: Inc_Synth generic map (n => 3)
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port map (a => l_int, sum => l_inc);
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-- outputs
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lout <= l_inc when (sel = '1') else l_int;
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dout <= d_int;
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xout <= x_int;
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end diq_wordlevel;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity Inc_Synth is
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generic (n: integer := 8);
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port (a: in std_logic_vector (n-1 downto 0);
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sum: out std_logic_vector (n-1 downto 0)
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);
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end Inc_Synth;
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architecture compact_inc of Inc_Synth is
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signal cx: std_logic_vector (n downto 0);
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begin
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cx <= ('0' & a) + '1';
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sum <= cx (n-1 downto 0);
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end compact_inc;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity Add_Synth is
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generic (n: integer := 8);
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port (a, b: in std_logic_vector (n-1 downto 0);
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sum: out std_logic_vector (n-1 downto 0);
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cin: in std_logic;
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comp: out std_logic );
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end Add_Synth;
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architecture compact of Add_Synth is
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signal cx: std_logic_vector (n downto 0);
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begin
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cx <= ('0' & a) + ('0' & b) + cin;
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sum <= cx (n-1 downto 0);
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comp <= cx(n-1);
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end compact;
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