54 lines
903 B
Verilog
54 lines
903 B
Verilog
module main ();
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reg [31:0] tdelay;
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reg [3:0] var1,var2;
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reg error;
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always @(var1)
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#tdelay var2 = var1;
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initial
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begin
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error = 0;
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tdelay = 5;
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# 1; // This removes race between tdelay5 and var2.
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var2 = 0;
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#1 ;
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var1 = 1; // Now twiddle var1 to cause var2 change 5ns later.
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#1 ;
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if(var2 != 0)
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begin
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$display("FAILED at %t",$time);
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error = 1;
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end
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#1;
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if(var2 != 0)
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begin
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$display("FAILED at %t",$time);
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error = 1;
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end
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#1;
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if(var2 != 0)
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begin
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$display("FAILED at %t",$time);
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error = 1;
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end
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#1;
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if(var2 != 0)
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begin
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$display("FAILED at %t",$time);
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error = 1;
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end
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#1;
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if(var2 != 1)
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begin
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$display("FAILED at %t",$time);
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error = 1;
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end
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if(error == 0)
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$display("PASSED");
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end
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endmodule
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