60 lines
1.1 KiB
Verilog
60 lines
1.1 KiB
Verilog
// Check that VAMS `abs()` functions works if its argument is a function call
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module main;
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function reg signed [7:0] fv(input reg signed [7:0] x);
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fv = x;
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endfunction
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function real fr(input real x);
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fr = x;
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endfunction
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reg signed [7:0] a;
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wire signed [7:0] vala = abs(fv(a));
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reg real b;
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wire real valb = abs(fr(b));
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initial begin
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a = 0;
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b = 0;
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#1 if (vala !== 0) begin
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$display("FAILED -- a=%b, vala=%b", a, vala);
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$finish;
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end
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#1 if (valb != 0) begin
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$display("FAILED -- b=%g valb=%g", b, valb);
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$finish;
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end
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a = 1;
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b = 1;
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#1 if (vala !== 1) begin
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$display("FAILED -- a=%b, vala=%b", a, vala);
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$finish;
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end
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#1 if (valb != 1) begin
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$display("FAILED -- b=%g valb=%g", b, valb);
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$finish;
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end
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a = -1;
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b = -1;
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#1 if (vala !== 1) begin
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$display("FAILED -- a=%b, vala=%b", a, vala);
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$finish;
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end
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#1 if (valb != 1) begin
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$display("FAILED -- b=%g valb=%g", b, valb);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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