20 lines
388 B
Verilog
20 lines
388 B
Verilog
// This tests that the individual bits of a uwire are checked for
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// double-driving individually. The code below is legal.
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module test;
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uwire [31:0] foo;
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assign foo[15:0] = 'haaaa;
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assign foo[31:16] = 'h5555;
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initial begin
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#1 if (foo !== 'h5555aaaa) begin
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$display("FAILED -- foo=%h", foo);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // test
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