22 lines
378 B
Verilog
22 lines
378 B
Verilog
module top;
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reg pass;
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uwire zero, one;
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assign one = 1'b1;
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initial begin
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pass = 1'b1;
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#1;
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if (zero !== 1'bz) begin
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$display("Failed: undriven uwire gave %b", zero);
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pass = 1'b0;
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end
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if (one !== 1'b1) begin
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$display("Failed: driven uwire gave %b", one);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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