73 lines
1.0 KiB
Verilog
73 lines
1.0 KiB
Verilog
// Copyright 2007, Martin Whitaker.
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// This code may be freely copied for any purpose.
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module unnamed_generate_block();
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localparam up = 1;
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wire [2:0] count1;
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wire [2:0] count2;
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wire [2:0] count3;
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generate
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if (up)
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count_up counter(count1);
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else
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count_down counter(count1);
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endgenerate
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generate
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if (up)
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begin:genblk1
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count_up counter(count2);
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end
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else
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begin:genblk1
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count_down counter(count2);
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end
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endgenerate
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count_down genblk01(count3);
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initial begin:genblk001
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reg [2:0] count;
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#1 count = 4;
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#1 count = 5;
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#1 count = 6;
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#1 count = 7;
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end
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always @(genblk0001.counter.count) begin
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$display(genblk0001.counter.count);
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end
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//initial begin
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// $dumpfile("dump.vcd");
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// $dumpvars;
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//end
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endmodule
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module count_up(output reg [2:0] count);
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initial begin
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#1 count = 0;
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#1 count = 1;
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#1 count = 2;
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#1 count = 3;
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end
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endmodule
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module count_down(output reg [2:0] count);
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initial begin
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#1 count = 3;
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#1 count = 2;
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#1 count = 1;
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#1 count = 0;
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end
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endmodule
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