26 lines
475 B
Verilog
26 lines
475 B
Verilog
module bug();
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reg [15 : 0] in;
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reg sel;
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wire [31 : 0] result = { 16'd0, sel ? -in : in };
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initial begin
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in = 100;
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sel = 0;
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#1 if (result !== 32'h0000_0064) begin
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$display("FAILED -- result=%h, sel=%b, in=%h", result, sel, in);
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$finish;
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end
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sel = 1;
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#1 if (result !== 32'h0000_ff9c) begin
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$display("FAILED == result=%h, sel=%b, in=%h, -in=%h",
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result, sel, in, -in);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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