94 lines
2.0 KiB
Verilog
94 lines
2.0 KiB
Verilog
/*
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* Copyright (c) 2000 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* This program checks that conbinational UDPs with x outputs are
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* properly executed.
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*/
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module main;
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wire Y;
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reg A, B, S;
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muxx1 MUX2 ( Y, S, A, B ) ;
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initial begin
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S = 0;
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A = 0;
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B = 0;
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#1 if (Y !== 1'b0) begin
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$display("FAILED -- Y is %b", Y);
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$finish;
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end
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B = 1;
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#1 if (Y !== 1'b0) begin
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$display("FAILED -- Y is %b", Y);
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$finish;
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end
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S = 1;
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#1 if (Y !== 1'b1) begin
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$display("FAILED -- Y is %b", Y);
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$finish;
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end
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B = 1'bx;
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#1 if (Y !== 1'bx) begin
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$display("FAILED -- Y is %b", Y);
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$finish;
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end
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B = 1;
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S = 1'bx;
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#1 if (Y !== 1'bx) begin
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$display("FAILED -- Y is %b", Y);
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$finish;
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end
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B = 0;
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#1 if (Y !== 1'b0) begin
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$display("FAILED -- Y is %b", Y);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule
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primitive muxx1(Q, S, A, B);
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output Q;
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input S, A, B;
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table
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// S A B Q
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0 0 ? : 0 ;
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0 1 ? : 1 ;
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0 x ? : x ; // problem line
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1 ? 0 : 0 ;
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1 ? 1 : 1 ;
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1 ? x : x ; // problem line
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x 0 0 : 0 ;
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x 1 1 : 1 ;
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endtable
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endprimitive
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