60 lines
1.1 KiB
Verilog
60 lines
1.1 KiB
Verilog
/*
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* This test tries to assure that all synchronous UDP outputs are
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* scheduled before any non-blocking assignment event. The reason
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* is that primitive outputs are scheduled in the active event
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* queue, which is supposed to empty before any non-blocking
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* assignments take effect.
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*
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* This is based on an example by Steve Sharp
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*/
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primitive u_dff(q,d,c);
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output q;
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reg q;
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input d,c;
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table
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//d c : q : q+
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0 p : ? : 0 ;
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1 p : ? : 1 ;
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? n : ? : - ;
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* ? : ? : - ;
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endtable
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endprimitive
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module top;
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reg rclk, dclk;
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wire clk = rclk;
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wire q0,q1,q2,q3,q4;
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u_dff ff0(q0, 1'b1, clk),
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ff1(q1, 1'b1, q0),
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ff2(q2, 1'b1, q1),
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ff3(q3, 1'b1, q2),
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ff4(q4, 1'b1, q3);
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initial
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begin
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#1
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// Blocking assign makes an active event that
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// starts the u_dff devices rippling
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rclk = 1;
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// Non-blocking assign and the following @(dclk) pause
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// the thread until the non-blocking event queue is
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// processed.
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dclk <= 1;
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@(dclk)
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if (q4 !== 1'b1) begin
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$display("FAILED -- q4 did not propagate in time (q4=%b)", q4);
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$finish;
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end
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$display("q4=%b", q4);
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$display("PASSED");
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end
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endmodule
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