55 lines
826 B
Verilog
55 lines
826 B
Verilog
`timescale 1ns/100ps
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primitive udp_and(
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output y,
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input a,
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input b
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);
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table
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//a b : y
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0 0 : 0 ;
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0 1 : 0 ;
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1 0 : 0 ;
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1 1 : 1 ;
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x 0 : 0 ;
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0 x : 0 ;
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endtable
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endprimitive
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module test();
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reg a;
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reg b;
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wire y;
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udp_and #0.5 gate(y, a, b);
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reg failed = 0;
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initial begin
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$monitor($realtime,,a,,b,,y);
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a = 0; b = 0;
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#0.6 if (y !== 1'b0) failed = 1;
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a = 1; b = 1;
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#0.4 if (y !== 1'b0) failed = 1;
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#0.2 if (y !== 1'b1) failed = 1;
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a = 0; b = 1;
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#0.4 if (y !== 1'b1) failed = 1;
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#0.2 if (y !== 1'b0) failed = 1;
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a = 1; b = 1;
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#0.4 if (y !== 1'b0) failed = 1;
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#0.2 if (y !== 1'b1) failed = 1;
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a = 1; b = 0;
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#0.4 if (y !== 1'b1) failed = 1;
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#0.2 if (y !== 1'b0) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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