55 lines
822 B
Verilog
55 lines
822 B
Verilog
module test;
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reg cp;
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reg d;
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wire q;
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dff ff(q, cp, d);
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always begin #5 cp=0; #5 cp=1; end
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always
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begin
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@(negedge cp)
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d <= ~d;
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@(posedge cp)
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if (q !== 'bx && d === q)
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begin
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$display("FAILED, d=%b, q=%b", d, q);
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#1 $finish;
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end
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end
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initial
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begin
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#1 d <= 1;
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#22;
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$display("PASSED");
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$finish;
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end
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initial $monitor($time,,cp,,d,,q);
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endmodule
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primitive dff(q, cp, d);
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output q;
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input cp, d;
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reg q;
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table
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// (cp) d : q : q ;
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? * : ? : - ;
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(?0) ? : ? : - ;
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(1x) ? : ? : - ;
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(x1) 0 : 0 : 0 ;
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(x1) 1 : 1 : 1 ;
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(0x) 0 : 0 : 0 ;
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(0x) 1 : 1 : 1 ;
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(01) 0 : ? : 0 ;
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(01) 1 : ? : 1 ;
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endtable
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endprimitive
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