38 lines
528 B
Verilog
38 lines
528 B
Verilog
// Check that it is possible to have a `output reg` in a UDP defintion
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module test;
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reg clk = 1'b0;
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reg d = 1'b0;
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wire q;
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dff ff(q, clk, d);
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initial begin
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#1
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clk = 1'b1;
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#1
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clk = 1'b0;
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d = 1'b1;
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if (q === 1'b0) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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primitive dff(q, c, d);
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output reg q;
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input c, d;
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table
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//c d : q : q+
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p 0 : ? : 0 ;
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p 1 : ? : 1 ;
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n ? : ? : - ;
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? * : ? : - ;
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endtable
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endprimitive
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