149 lines
3.5 KiB
Verilog
149 lines
3.5 KiB
Verilog
/*
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* Copyright (c) 2001 Stephan Boettcher <stephan@nevis.columbia.edu>
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// $Id: udp_lfsr.v,v 1.1 2001/10/27 23:38:29 sib4 Exp $
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module test_lfsr;
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reg cp;
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reg in;
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wire out;
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reg reset;
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lfsr sr(cp, reset, in, out);
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reg errors;
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initial errors = 0;
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integer i;
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initial
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begin
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in = 0;
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cp = 0;
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#2 reset = 1;
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#2 reset = 0;
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#1;
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for (i=0; i<512; i=i+1)
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#5 cp = ~cp;
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in = 0;
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cp = 0;
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#2 reset = 1;
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#2 reset = 0;
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#1;
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for (i=0; i<512; i=i+1)
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#5 cp <= ~cp;
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#5;
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if (errors == 0)
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$display("PASSED");
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#10 $finish;
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end
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reg [7:0] here;
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reg [7:0] next;
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reg [7:0] old;
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reg [7:0] new;
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always @(reset)
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if (reset)
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begin
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here = 1;
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#1;
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old = {out, sr.s};
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if (old === here)
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begin
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$display("%b RESET", old);
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end
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else
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begin
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$display("%b RESET FAILED: expect %b", old, here);
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errors = 1;
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end
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end
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always
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begin
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@(posedge cp) old = {out, sr.s};
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next = {here[6:0], ^(here & sr.P) ^ in};
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@(negedge cp) new = {out, sr.s};
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if (old != here || new !== next)
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begin
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$display("%b->%b FAILED: expect %b->%b", old, new, here, next);
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errors = 1;
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end
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else
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begin
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$display("%b->%b", old, new);
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end
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here = next;
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end
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endmodule
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module lfsr (clk, reset, in, out);
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parameter P = 8'b 1101_1001;
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input clk;
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input reset;
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input in;
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output out;
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wire [6:0] s;
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wire i = ^{P & {out,s}} ^ in;
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jkff ff1 (s[0], clk, i, ~i, reset, 0);
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jkff ff2 (s[1], clk, s[0], ~s[0], 0, reset);
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jkff ff3 (s[2], clk, s[1], ~s[1], 0, reset);
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jkff ff4 (s[3], clk, s[2], ~s[2], 0, reset);
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jkff ff8 (out, clk, s[6], ~s[6], 0, reset);
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jkff ff7 (s[6], clk, s[5], ~s[5], 0, reset);
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jkff ff6 (s[5], clk, s[4], ~s[4], 0, reset);
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jkff ff5 (s[4], clk, s[3], ~s[3], 0, reset);
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endmodule
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primitive jkff(q, cp, j, k, s, r);
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output q;
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input cp, j, k, s, r;
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reg q;
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table
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// (cp) j k s r : q : q ;
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? ? ? (?0) 0 : ? : - ;
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? ? ? 0 (?0) : ? : - ;
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? * ? 0 0 : ? : - ;
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? ? * 0 0 : ? : - ;
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? ? ? 1 0 : ? : 1 ;
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? ? ? 0 1 : ? : 0 ;
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? ? ? x 0 : 1 : 1 ;
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? ? ? 0 x : 0 : 0 ;
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(?0) ? ? 0 0 : ? : - ;
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(1x) ? ? 0 0 : ? : - ;
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(?1) 0 ? 0 0 : 0 : 0 ;
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(?1) ? 0 0 0 : 1 : 1 ;
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(0x) 0 ? 0 0 : 0 : 0 ;
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(0x) ? 0 0 0 : 1 : 1 ;
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(01) 1 ? 0 0 : 0 : 1 ;
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(01) ? 1 0 0 : 1 : 0 ;
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(01) 1 0 0 0 : x : 1 ;
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(01) 0 1 0 0 : x : 0 ;
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endtable
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endprimitive
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