49 lines
791 B
Verilog
49 lines
791 B
Verilog
module top;
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reg pass;
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tri ctl;
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reg in0, in1;
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wire out;
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integer a;
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// Code to force two drivers.
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pullup (ctl);
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assign ctl = a ? 1'bz : 1'b0;
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mux2 q1(out, ctl, in0, in1);
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initial begin
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pass = 1'b1;
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a = 0;
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in0 = 1'b0;
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in1 = 1'b1;
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#1;
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if (out !== 1'b0) begin
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$display("Failed UDP with ctl 0, expected 1'b0, got %b", out);
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pass = 1'b0;
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end
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a = 1;
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#1;
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if (out !== 1'b1) begin
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$display("Failed UDP with ctl 1, expected 1'b1, got %b", out);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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primitive mux2 (out, ctl, in0, in1);
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output out;
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input ctl, in0, in1;
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table
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0 0 ? : 0;
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0 1 ? : 1;
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1 ? 0 : 0;
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1 ? 1 : 1;
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x 0 0 : 0;
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x 1 1 : 1;
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endtable
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endprimitive
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