93 lines
2.0 KiB
Verilog
93 lines
2.0 KiB
Verilog
/*
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* udp_dff.v
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* This is based on a bug report from Chacko Neroth. The original
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* compalint was that the (b0) in the table generated a syntax error
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* message.
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*/
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module test;
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reg dd, clk;
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wire qq;
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dff d1 (.Q(qq), .C(clk), .D(dd));
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initial begin
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dd = 1'b0;
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clk= 0;
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#1 clk = 1;
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#1 if (qq !== 1'b0) begin
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$display("FAILED -- D=%b, Q=%b", dd, qq);
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$finish;
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end
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dd = 1'b1;
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clk = 0;
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#1 if (qq !== 1'b0) begin
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$display("FAILED -- D=%b (hold 0), Q=%b", dd, qq);
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$finish;
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end
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clk = 1;
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#1 if (qq !== 1'b1) begin
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$display("FAILED -- D=%b, Q=%b", dd, qq);
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$finish;
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end
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dd = 1'bx;
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clk = 0;
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#1 if (qq !== 1'b1) begin
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$display("FAILED -- D=%b (hold 1), Q=%b", dd, qq);
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$finish;
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end
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clk = 1;
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#1 if (qq !== 1'bx) begin
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$display("FAILED -- D=%b, Q=%b", dd, qq);
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$finish;
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end
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dd = 1'bz;
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clk = 0;
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#1 if (qq !== 1'bx) begin
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$display("FAILED -- D=%b (hold x), Q=%b", dd, qq);
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$finish;
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end
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clk = 1;
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#1 if (qq !== 1'bx) begin
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$display("FAILED -- D=%b, Q=%b", dd, qq);
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$finish;
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end
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dd = 1'b0;
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clk = 0;
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#1 if (qq !== 1'bx) begin
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$display("FAILED -- D=%b (hold x), Q=%b", dd, qq);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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primitive dff (Q, C, D, notifier);
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output Q;
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reg Q;
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input C, D, notifier;
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table
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// C D notifier : Q : Q+
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(01) 0 ? : ? : 0 ; //normal clocking case
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(01) 1 ? : ? : 1 ; //normal clocking case
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(01) x ? : ? : x ; //normal clocking, input undefined
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(b0) ? ? : ? : - ; //clock falling or held low
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// if the above is changed to the following, it goes thru
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// (10) ? ? : ? : - ; //clock falling
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// but the following, which (b0) should iterate to fails also
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// (00) ? ? : ? : - ; //clock held low
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b (??) ? : ? : - ; //hold Q if D changes
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? ? * : ? : x ; //notifier case
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endtable
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endprimitive
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