42 lines
772 B
Verilog
42 lines
772 B
Verilog
/*
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* This is a simplified version of the test program for issue 1323691
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* from the iverilog bugs database.
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*/
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`timescale 1ns/1ns
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module main;
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parameter early_empty=1;
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reg re;
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reg rc_isEmpty, rc_willBeEmpty;
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wire empty;
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assign empty = (early_empty!=0) ?
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rc_willBeEmpty && re || rc_isEmpty :
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rc_isEmpty;
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initial begin
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rc_isEmpty <= 1'bx;
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rc_willBeEmpty <= 1'b1;
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re <= 1'b0;
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rc_isEmpty <= 1'b0;
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#1 if (empty !== 1'b0) begin
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$display("FAILED -- empty == %b (s.b. 0)", empty);
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$finish;
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end
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rc_isEmpty <= 1;
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#1 if (empty !== 1'b1) begin
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$display("FAILED -- empty == %b (s.b. 1)", empty);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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