35 lines
1.0 KiB
Verilog
35 lines
1.0 KiB
Verilog
//
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// Copyright (c) 2003 Steve Williams
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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`timescale 1ns / 1ps
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module main;
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task test;
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$display("time within task: %t", $time);
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endtask // test
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initial begin
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$timeformat(-9, 3, "ns", 6);
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#1 $display("time within module: %t", $time);
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test;
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end
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endmodule
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