79 lines
1.9 KiB
Verilog
79 lines
1.9 KiB
Verilog
/*
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* Copyright (c) 2000 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* This program tests that a non-integer delay, in the absence of any
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* timescale values, will round properly. A 2.4 delay rounds to 2, and
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* a 2.6 delay rounds to 3.
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*/
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module main;
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reg clk;
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reg out1, out2;
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time time1;
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time time2;
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always @(posedge clk) #2.4 begin
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$display($time,, "set out1 == 1");
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time1 = $time;
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out1 = 1;
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end
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always @(posedge clk) #2.6 begin
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$display($time,, "set out2 == 1");
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time2 = $time;
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out2 = 1;
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end
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initial begin
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clk = 0;
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out1 = 0;
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out2 = 0;
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time1 = 0;
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time2 = 0;
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#1 if (out1 !== 0) begin
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$display("FAILED -- out1 is not 0: %b", out1);
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$finish;
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end
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clk = 1;
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#3 if (out1 !== 1) begin
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$display("FAILED -- out is not 1 at time 3: %b", out1);
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$finish;
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end
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if (time1 != 3) begin
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$display("FAILED -- time1 = %d", time1);
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$finish;
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end
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#1 if (time2 != 4) begin
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$display("FAILED -- time2 = %d", time2);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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