36 lines
756 B
Verilog
36 lines
756 B
Verilog
module main;
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reg [1:0] src;
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wire [3:0] dst, dst2, dst3;
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foo_entity dut (.data_o(dst), .data_o2(dst2), .data_o3(dst3), .data_i(src));
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initial begin
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src = 2'b00;
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#1 if (dst != 4'b0001 || dst2 != 4'bxxxx || dst3 != 4'bxxx) begin
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$display("FAILED");
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$finish;
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end
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src = 2'b01;
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#1 if (dst != 4'b0010 || dst2 != 4'b0101 || dst3 != 4'b0011) begin
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$display("FAILED");
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$finish;
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end
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src = 2'b10;
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#1 if (dst != 4'b0100 || dst2 != 4'b0101 || dst3 != 4'b1100) begin
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$display("FAILED");
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$finish;
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end
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src = 2'b11;
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#1 if (dst != 4'b1000 || dst2 != 4'b0101 || dst3 != 4'b1100) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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