59 lines
1000 B
Verilog
59 lines
1000 B
Verilog
// This module generate all 8 inputs for three boolean variables
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module stimulus #(parameter M = 8, T = 10) (
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output reg i0, i1,
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output reg s
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);
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bit [2:0] i;
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initial begin
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for (i = 0; i < M; i=i+1) begin
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#T;
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{i0, i1, s} = i;
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end
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#T;
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end
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endmodule
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// This module always checks the internal generated muxed output complies with the received one
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module check (input i0, i1, s, y);
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logic y_check;
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always @(i0, i1, s)
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y_check = s ? i1 : i0;
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always @(y, y_check) begin
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#1 if (y != y_check) begin
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$display("ERROR");
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$finish;
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end
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end
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endmodule
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module test;
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parameter M = 8;
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parameter T = 10;
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parameter S = (M+1)*T + 40;
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wire i0, i1, s, y;
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stimulus #(M, T) stim (.i0(i0), .i1(i1), .s(s) );
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mux2to1 duv (.i0(i0), .i1(i1), .s(s), .y(y) );
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check check (.i0(i0), .i1(i1), .s(s), .y(y) );
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initial begin
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#S;
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$display("PASSED");
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$finish;
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end
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endmodule
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