31 lines
650 B
Verilog
31 lines
650 B
Verilog
module main;
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parameter WIDTH = 8;
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parameter ITERATIONS = 1000;
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reg [WIDTH-1:0] src0, src1, ref_dst;
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reg clk;
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wire [WIDTH-1:0] dst;
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test #(.width(WIDTH)) test0 (.dst(dst), .src0(src0), .src1(src1), .clk(clk));
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integer idx;
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initial begin
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clk = 0;
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for (idx = 0 ; idx < ITERATIONS ; idx = idx+1) begin
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src0 = $random;
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src1 = $random;
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ref_dst = src0 ^ src1;
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#1 clk = 1;
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#1 if (dst !== ref_dst) begin
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$display("FAILED: src0=%b, src1=%b dst=%b, ref=%b",
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src0, src1, dst, ref_dst);
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$finish;
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end
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clk = 0;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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