108 lines
2.3 KiB
Verilog
108 lines
2.3 KiB
Verilog
/***************************************************************
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** Author: Oswaldo Cadenas (oswaldo.cadenas@gmail.com)
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** Date: September 27 2011
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**
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** Test: Intended to test the vhd code in enumsystem.vhd
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**
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** A stimulus modules generates a count 0,1,.., 7, 1 and an enable signal
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** A scoreboard forces a check according to the operation found in enumsystem.vhd
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**
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** The test runs for sometime making sure relevant input conditions are met throughout
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**************************************************************************************/
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module stim (input clk, reset, output reg [2:0] count, output reg en);
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always @(posedge clk) begin
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if (reset) count <= 3'b0;
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else count <= count + 1;
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end
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initial begin
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en = 1;
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repeat (100) @(posedge clk);
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en = 0;
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end
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endmodule
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module scoreboard (input [2:0] count, input reset, en, input [0:3] y);
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initial begin
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@(posedge reset);
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@(negedge reset); // waiting for reset to become inactive
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mycheck();
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end
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task mycheck;
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forever begin
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#1;
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if (en == 0) begin
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if (y !== 4'b0000) begin
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$display ("ERROR");
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$finish;
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end
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end
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else begin
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#2;
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case (count)
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0: if (y !== 4'b1000) begin
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$display("ERROR");
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$finish;
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end
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1: if (y !== 4'b0100) begin
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$display("ERROR");
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$finish;
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end
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2: if (y !== 4'b0010) begin
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$display("ERROR");
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$finish;
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end
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3: if (y !== 4'b0001) begin
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$display("ERROR");
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$finish;
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end
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default: if (y !== 4'b1111 && en == 1) begin
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$display("ERROR here, en = %d", en);
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$finish;
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end
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endcase
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end // else
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end // always
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endtask
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endmodule
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module test;
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parameter T = 10;
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parameter S = 2*10*150;
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bit clk = 0, reset = 0;
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wire en;
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wire [2:0] count;
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wire [0:3] y;
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initial forever #(T) clk = !clk;
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initial begin
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@(negedge clk);
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reset = 1'b1;
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repeat(6) @(negedge clk);
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reset = 1'b0;
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end
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stim stim (.clk(clk), .reset(reset), .en(en), .count(count) );
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enumsystem duv (.clk(clk), .reset(reset), .en(en), .y(y) );
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scoreboard check (.en(en), .reset(reset), .count(count), .y(y) );
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initial begin
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#S;
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$display("PASSED");
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$finish;
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end
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endmodule
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