50 lines
1.5 KiB
Verilog
50 lines
1.5 KiB
Verilog
/*
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* Copyright (c) 2000 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.will need a Picture Elements Binary Software
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* License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/*
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* This program catches some glitches in the MUXZ that Icarus Verilog
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* uses to implement the ?: in structural cases.
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*/
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module main;
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reg [6:0] a, b;
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reg sel;
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wire [6:0] test = sel? a : b;
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wire [7:0] test2 = test;
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initial begin
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sel = 0;
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// At this point, test2 should be x.
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#1 $display("sel=%b, test2=%b", sel, test2);
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b = 0;
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#1 $display("sel=b, test2=%b", sel, test2);
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if (test2 !== 8'b0_0000000) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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