48 lines
1.0 KiB
Verilog
48 lines
1.0 KiB
Verilog
/*
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*/
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module main();
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reg [8:0] foo;
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reg [1:0] bar;
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initial begin
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foo = 2'b00 ? 9'b000111xxx : 9'b01x01x01x;
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$display("00: foo = %b", foo);
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foo = 2'b01 ? 9'b000111xxx : 9'b01x01x01x;
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$display("01: foo = %b", foo);
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foo = 2'b0x ? 9'b000111xxx : 9'b01x01x01x;
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$display("0x: foo = %b", foo);
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foo = 2'b11 ? 9'b000111xxx : 9'b01x01x01x;
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$display("11: foo = %b", foo);
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foo = 2'b1x ? 9'b000111xxx : 9'b01x01x01x;
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$display("1x: foo = %b", foo);
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bar = 2'b00;
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foo = bar? 9'b000111xxx : 9'b01x01x01x;
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$display("%b: foo = %b", bar, foo);
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bar = 2'b01;
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foo = bar? 9'b000111xxx : 9'b01x01x01x;
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$display("%b: foo = %b", bar, foo);
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bar = 2'b0x;
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foo = bar? 9'b000111xxx : 9'b01x01x01x;
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$display("%b: foo = %b", bar, foo);
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bar = 2'b11;
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foo = bar? 9'b000111xxx : 9'b01x01x01x;
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$display("%b: foo = %b", bar, foo);
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bar = 2'b1x;
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foo = bar? 9'b000111xxx : 9'b01x01x01x;
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$display("%b: foo = %b", bar, foo);
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end
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endmodule
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