28 lines
741 B
Verilog
28 lines
741 B
Verilog
module test;
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reg [0:0] stat;
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initial begin
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stat = 1'b0;
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// This should display (Start).
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$display("(%s)", stat[0] ? "Stop" : "Start");
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// This should also display (Start). It's been known
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// to display (tart) by getting the expression width
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// from the true clause.
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$display("(%s)", !stat[0] ? "Start" : "Stop");
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$display("$bits == %0d", $bits(stat[0] ? "Stop" : "Start"));
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if ($bits(stat[0] ? "Stop" : "Start") !== 40) begin
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$display("FAILED");
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$finish;
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end
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$display("$bits == %0d", $bits(stat[0] ? "Start" : "Stop"));
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if ($bits(stat[0] ? "Start" : "Stop") !== 40) begin
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$display("FAILED");
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$finish;
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end
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end
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endmodule
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