24 lines
417 B
Verilog
24 lines
417 B
Verilog
/*
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* This program doesn't do anything, and shouldn't be run. This is
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* only to check that the null target can see the ternary operator.
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*/
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module main2( );
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reg sel;
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reg [13:0] out;
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reg [13:0] a, b;
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// This assign works OK
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// assign out[13:0] = ( sel ? a[13:0] : b[13:0] );
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always @(
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sel or
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a or
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b
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)
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begin
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out[13:0] = ( sel ? a[13:0] : b[13:0] );
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end
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endmodule
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