18 lines
344 B
Verilog
18 lines
344 B
Verilog
// Check that it is an error to declare a non-ANSI task port with implicit
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// packed dimensions if it is later redeclared as a vector typed variable and
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// the size of the packed dimensions do not match.
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module test;
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task t;
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input [7:0] x;
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reg [3:0] x;
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$display("FAILED");
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endtask
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initial begin
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t(10);
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end
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endmodule
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