29 lines
507 B
Verilog
29 lines
507 B
Verilog
// Check that it is possible to declare the data type for a struct type task
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// port before the direction for non-ANSI style port declarations.
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module test;
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typedef struct packed {
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reg [31:0] x;
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reg [7:0] y;
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} T;
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task t;
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input x;
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T x;
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if (x.x == 10 && x.y == 20 && $bits(x) == $bits(T)) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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endtask
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initial begin
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static T val;
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val.x = 10;
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val.y = 20;
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t(val);
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end
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endmodule
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