16 lines
310 B
Verilog
16 lines
310 B
Verilog
// Check that declaring an integer typed variabe for a signal that was
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// previously declared as a non-ANSI task port is an error. Even if the types
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// for both declarations are the same.
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module test;
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task t;
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input integer x;
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integer x;
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$display("FAILED");
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endtask
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initial t();
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endmodule
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