43 lines
745 B
Verilog
43 lines
745 B
Verilog
module automatic test();
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task static accumulate1(input integer value, output integer result);
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static int acc = 1;
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acc = acc + value;
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result = acc;
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endtask
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task accumulate2(input integer value, output integer result);
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int acc = 1;
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acc = acc + value;
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result = acc;
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endtask
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integer value;
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reg failed = 0;
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initial begin
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accumulate1(2, value);
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$display("%d", value);
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if (value !== 3) failed = 1;
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accumulate1(3, value);
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$display("%d", value);
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if (value !== 6) failed = 1;
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accumulate2(2, value);
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$display("%d", value);
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if (value !== 3) failed = 1;
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accumulate2(3, value);
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$display("%d", value);
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if (value !== 4) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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