22 lines
428 B
Verilog
22 lines
428 B
Verilog
module main;
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// The declaration assignment within a task it not allowed
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// in Verilog, but it is allowed in SystemVerilog.
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task foo (input integer x, output integer y);
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integer step = 3;
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y = x + step;
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endtask // foo
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integer a, b;
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initial begin
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a = 3;
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foo(a, b);
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if (b !== 6) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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