72 lines
1.4 KiB
Verilog
72 lines
1.4 KiB
Verilog
/*
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* Copyright (c) 2000 Stephan I. Boettcher <stephan@nevis.columbia.edu>
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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// compile time test for nested task scope elaboration
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`define TEST
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module nest(r);
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output [7:0] r;
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reg [7:0] r;
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task incr;
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input [7:0] a;
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begin
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r <= r+a;
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#1 $display("R=%b",r);
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end
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endtask
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endmodule
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module test;
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wire [7:0] acc;
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nest n(acc);
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initial n.r <= 0;
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`ifdef TEST
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task increment;
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begin
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n.incr(1);
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end
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endtask
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`endif
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initial
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begin
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`ifdef TEST
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#10 increment;
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#10 increment;
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#10 increment;
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`else
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#10 n.incr(3);
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`endif
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#10;
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if (acc==3)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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