117 lines
3.1 KiB
Verilog
117 lines
3.1 KiB
Verilog
/* talu - a verilog test,
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* illustrating problems I had in fragments of an ALU from an 8-bit micro
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*/
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module talu;
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reg error;
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reg [7:0] a;
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reg [7:0] b;
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reg cin;
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reg [1:0] op;
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wire cout;
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wire [7:0] aluout;
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alu alu_m(a, b, cin, op, aluout, cout);
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initial begin
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error = 0;
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// add
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op='b00; cin='b0; a='h0; b='h0;
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#2 if({cout, aluout} != 9'h000) begin
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$display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout);
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error = 1;
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end
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// add1
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op='b01; cin='b0; a='h01; b='h01;
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#2 if({cout, aluout} != 9'h103) begin
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$display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout);
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error = 1;
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end
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// and
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op='b10; cin='b0; a='h16; b='h0F;
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#2 if({cout, aluout} != 9'h006) begin
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$display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout);
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error = 1;
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end
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op='b10; cin='b0; a='h28; b='hF7;
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#2 if({cout, aluout} != 9'h020) begin
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$display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout);
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error = 1;
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end
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// genbit
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op='b11; cin='b0; a='h00; b='h03;
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#2 if({cout, aluout} != 9'h008) begin
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$display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout);
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error = 1;
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end
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op='b11; cin='b0; a='h00; b='h00;
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#2 if({cout, aluout} != 9'h001) begin
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$display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout);
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error = 1;
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end
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/* tests are incomplete - doesn't compile yet on ivl */
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if(error == 0)
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$display("PASSED");
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$finish;
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end
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endmodule
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/*
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* fragments of an ALU from an 8-bit micro
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*/
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module alu(Aval, Bval, cin, op, ALUout, cout);
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input [7:0] Aval;
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input [7:0] Bval;
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input cin;
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input [1:0] op;
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output cout;
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output [7:0] ALUout;
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reg cout;
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reg [7:0] ALUout;
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always @(Aval or Bval or cin or op) begin
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case(op)
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2'b00 : {cout, ALUout} = Aval + Bval;
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2'b10 : {cout, ALUout} = {1'b0, Aval & Bval};
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// C++ compilation troubles with both of these:
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2'b01 : {cout, ALUout} = 9'h100 ^ (Aval + Bval + 9'h001);
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2'b11 : {cout, ALUout} = {1'b0, 8'b1 << Bval};
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// 2'b01 : {cout, ALUout} = 9'h000;
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// 2'b11 : {cout, ALUout} = 9'h000;
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endcase
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end // always @ (Aval or Bval or cin or op)
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endmodule
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/* Copyright (C) 1999 Stephen G. Tell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this software; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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* Boston, MA 02111-1307 USA
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*/
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