58 lines
581 B
Verilog
58 lines
581 B
Verilog
package my_package1;
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parameter p1 = 1;
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localparam p2 = 2;
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typedef logic [1:0] word;
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word v;
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event e;
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function word f(word g);
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f = g + 1;
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endfunction
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task h(word i);
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v = v + i;
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$display(v);
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endtask
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endpackage
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package my_package2;
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parameter p1 = 1;
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localparam p2 = 2;
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typedef logic [1:0] word;
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word v;
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event e;
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function word f(word g);
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f = g + 1;
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endfunction
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task h(word i);
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v = v + i;
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$display(v);
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endtask
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endpackage
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module test();
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import my_package1::*;
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import my_package2::*;
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word my_v;
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initial begin
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@(e) v = p1 + p2;
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h(f(1));
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end
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endmodule
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