67 lines
757 B
Verilog
67 lines
757 B
Verilog
package my_package;
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parameter p1 = 1;
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localparam p2 = p1 + 'bx;
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typedef logic [1:0] word;
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word v = 2'bx;
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event e;
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function word f(word g);
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f = g + 2'bx;
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endfunction
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task h(word i);
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v = v + i + 2'bx;
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$display(v);
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endtask
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endpackage
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module test();
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import my_package::*;
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parameter p1 = 3;
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localparam p2 = p1 + 2;
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typedef logic [7:0] word;
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word v = 0;
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event e;
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word my_v = 0;
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initial begin
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#1 ->my_package::e;
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end
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initial begin
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@(my_package::e);
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my_v = p1;
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#1 ->e;
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end
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initial begin
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@e v = my_v;
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h(f(1));
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if (p2 === 5 && $bits(v) === 8 && v === 5)
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$display("PASSED");
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else
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$display("FAILED");
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end
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function word f(word g);
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f = g + 1;
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endfunction
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task h(word i);
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v = v + i;
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$display(v);
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endtask
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endmodule
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