51 lines
881 B
Verilog
51 lines
881 B
Verilog
// Check that the var keyword is supported for variable declarations in blocks
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, `"val`", val, exp); \
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failed = 1'b1; \
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end
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module test;
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bit failed = 1'b0;
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initial begin
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var x;
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var [7:0] y;
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var signed [8:0] z;
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var logic [9:0] w;
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x = 1'b1;
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y = 8'd10;
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z = -8'sd1;
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w = 8'd20;
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`check(x, 1'b1)
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`check(y, 10)
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`check(z, -1)
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`check(w, 20)
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// var should default to logic and allow x state
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x = 1'bx;
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y = 8'hxx;
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z = 8'hxx;
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w = 8'hxx;
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`check(x, 1'bx)
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`check(y, 8'hxx)
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`check(z, 8'hxx)
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`check(w, 8'hxx)
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`check($bits(x), 1)
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`check($bits(y), 8)
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`check($bits(z), 9)
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`check($bits(w), 10)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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