44 lines
769 B
Verilog
44 lines
769 B
Verilog
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// output ports may be uwire, or even a variable, if wire-ness
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// or variable-ness are not explicitly stated.
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typedef struct packed {
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logic [1:0] a;
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logic [1:0] b;
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} sample_t;
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module main;
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sample_t dst;
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logic [1:0] src_a, src_b;
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DUT dut(.out(dst), .x(src_a), .y(src_b));
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initial begin
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src_a = 1;
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src_b = 2;
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#1 /* wait for dst */;
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if (dst.a !== 1) begin
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$display("FAILED -- dst.a=%b (dst=%b)", dst.a, dst);
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$finish;
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end
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if (dst.b !== 2) begin
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$display("FAILED -- dst.b=%b (dst=%b)", dst.b, dst);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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module DUT(output sample_t out,
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input logic [1:0] x, y);
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always @* begin
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out.a = x;
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out.b = y;
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end
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endmodule
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