31 lines
666 B
Verilog
31 lines
666 B
Verilog
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// This simple program tests that a variable can be assigned
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// party by continuous assignment, and partly by behavioral
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// assignment. As long as the parts don't overlap, this is
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// legal (in SystemVerilog)
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module main;
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logic [3:0] foo;
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// Part of the vector is assigned by continuous assignment
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logic [1:0] bar;
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assign foo[2:1] = bar;
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initial begin
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// Part of the vector is assigned behaviorally.
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foo[0] = 1'b1;
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foo[3] = 1'b1;
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bar = 2'b00;
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#1 if (foo !== 4'b1001) begin
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$display("FAILED -- foo=%b", foo);
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$finish;
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end
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$display("PASSED");
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$finish;
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end // initial begin
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endmodule // main
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