37 lines
595 B
Verilog
37 lines
595 B
Verilog
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module TEST
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#(parameter ME = 0)
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(input OE,
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output wire [3:0] Q
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/* */);
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assign Q = OE? ME : 4'd0;
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endmodule // TEST
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module main;
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logic OE;
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logic [3:0] Q [0:3];
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genvar gidx;
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for (gidx = 0 ; gidx < 4 ; gidx = gidx+1) begin : DRV
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TEST #(.ME(gidx)) dut (.OE(OE), .Q(Q[gidx]));
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end
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int idx;
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initial begin
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OE = 1;
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#1 ;
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for (idx = 0 ; idx < 4 ; idx = idx+1) begin
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if (Q[idx] !== idx[3:0]) begin
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$display("FAILED -- Q[%0d] === %b", idx, Q[idx]);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule // main
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